This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-288330, filed Sep. 22, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory, and more particularly to a Flash memory with multi-level cells used for 2-level/4-level switchable Flash memory.
2. Description of the Related Art
Flash memories with two levels (hereinafter denoted by 2-level data) have been widely used. However, when Flash memories with three or more levels (multi-level), for example, 4-level (hereinafter denoted by 4-level data) are produced, characteristics of reference cells and increase of an area of sense amplifiers will become serious problems. These problems will be described below.
FIG. 23 shows two threshold voltage distributions of a Flash memory which includes an array of memory cells (2-level cells) capable of storing 2-level data xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d.
FIG. 24 also shows four threshold voltage distributions of a Flash memory which includes an array of memory cells (4-level cells) capable of storing 4-level data xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d, xe2x80x9c2xe2x80x9d and xe2x80x9c3xe2x80x9d. This has been already disclosed in M. Bauer et al., xe2x80x9cA multi-level cell 32 Mb Flash memory,xe2x80x9d ISSCC digest of technical papers, pp. 132-3, 1995.
It will be understood from FIGS. 23 and 24 that the distribution width and interval of the threshold voltages must be tight in the 4-level cells as compared with the 2-level cells.
FIG. 25 shows a relation between agate voltage Vg and a drain current Id (cell current per unit load current) in both memory cells and reference cells of 2-level cell Flash memory.
In the Vg-Id characteristics of the memory cells, data xe2x80x9c1xe2x80x9d are given when the number of electrons stored in a floating gate is comparatively large, namely, the threshold voltage Vth is high, and data xe2x80x9c0xe2x80x9d are given when the number of electrons thereof is comparatively small, namely, the threshold voltage Vth is low. That is, the memory cells storing data xe2x80x9c1xe2x80x9d are denoted by cells xe2x80x9c1xe2x80x9d, while the memory cells storing data xe2x80x9c0xe2x80x9d are denoted by cells xe2x80x9c0xe2x80x9d.
The cell current Iref flowing through the reference cell is approximately half as compared with the cell current Icell of the memory cell. That is, the current Iref of the reference cell is set so as to have approximately half of the cell current cell of the memory cell. Accordingly, the difference between the cell currents Icell and Iref is approximately equal in xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d when the gate voltage is equal to a read voltage. The current difference is converted into a voltage difference, thereby reading out cell data by a sense amplifier for providing digital signals of xe2x80x9c0xe2x80x9d/xe2x80x9c1xe2x80x9d.
FIG. 26 represents Vg-Id characteristics of the memory cells in 4-level Flash memories, which shows portions corresponding to a part (0xe2x80x9d, xe2x80x9c1xe2x80x9d, xe2x80x9c2xe2x80x9d) of 4-level data xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d, xe2x80x9c2xe2x80x9d and xe2x80x9c3xe2x80x9d.
In FIG. 26, twelve characteristics show those of upper and lower limits in respective distributions of data xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d and xe2x80x9c2xe2x80x9d for every two characteristics in the case of high and low temperatures. It will be apparent that the temperature dependence of the Vg-Id characteristics of the cell current Icell is considerably high.
If the characteristics of 2-level reference cell are applied to those of 4-level reference cell as it is, the temperature change in Iref will become halt of that in Icell, because Icell is about half of Icell as described above.
Icell have the highest temperature change in the case where it corresponds to xe2x80x9c0xe2x80x9d, while having the lowest temperature change in the case where it corresponds to xe2x80x9c3xe2x80x9d (not shown). This means that the characteristics of conventional 2-level reference cells are applied in the case of xe2x80x9c3xe2x80x9d as it is, but that those of 2-level reference cells are not applied in the case of xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d and xe2x80x9c2xe2x80x9d, respectively.
Since three sense amplifiers are required in order to enable that 4-level cells are readout in the memories for reading 2-level cells as disclosed in C. Calligaro et al., xe2x80x9cComparative analysis of sensing schemes for multilevel non-volatile memories,xe2x80x9d Proceedings of Second Annual IEEE International conference on innovative systems in silicon, pp 266-73, 1997, the area of the memories will be increased as compared with that of 2-level cell memories.
In the conventional non-volatile memories, as described above, when the characteristics of 2-level reference cells are applied in the case of 4-level cells as it is, the conventional technique can be applied to data xe2x80x9c3xe2x80x9d, but can not be applied to data xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d and xe2x80x9c2xe2x80x9d, respectively. Further, when the memory cells are provided to have a switchable mode of 2-level mode/4-level mode, thereby reading out the 4-level mode, the area of the sense amplifiers will be increased as compared with the case for reading out the 2-level cells.
According to a first aspect of the present invention, there is provided a non-volatile semiconductor memory which comprises a memory cell array having a plurality of non-volatile memory cells;
word lines, bit lines and source lines connected to the memory cells;
a row decoder for selecting one of the word lines;
a column decoder for selecting one of the bit lines;
at least one reference cell;
a read circuit for reading data by applying a first voltage to one of the word lines to compare a current flowing through one of the bit lines with a current flowing through the reference cell;
an erase circuit for erasing the data by applying a voltage to at least two selected from the word lines, the bit lines, the source lines and a semiconductor region including the memory cells;
first and second regulators; and
an erase verify circuit for detecting whether the erase has finished by applying an output voltage of the first regulator to word lines of the memory cells to be erased, while applying an output voltage of the second regulator to a word line of the reference cell, thereby comparing a cell current of selected one of the memory cells with a cell current of the reference cell.
According to a second aspect of the present invention, there is provided a non-volatile semiconductor memory which comprises a memory cell array having a plurality of non-volatile memory cells;
word lines, bit lines and source lines connected to the memory cells;
a row decoder for selecting one of the word lines;
a column decoder for selecting one of the bit lines;
at least one reference cell;
a read circuit for reading data by applying a first voltage to one of the word lines to compare a current flowing through one of the bit lines with a current flowing through the reference cell;
a program circuit for programming the data by applying a voltage to at least two selected from the word lines, the bit lines, the source lines and a semiconductor region including the memory cells;
first and second regulators; and
a program verify circuit for detecting whether programming has finished by applying an output voltage of the second regulator to word lines of the memory cells to be programmed, while applying an output voltage of the second regulator to a word line of the reference cell, thereby comparing a cell current of selected one of the memory cells with a cell current of the reference cell.
According to the first and second non-volatile semiconductor memories, a word line voltage control circuit for controlling a word line voltage Vwl of the memory cells can be basically provided with the same structure as a reference word line voltage control circuit for controlling a word line voltage Vwlref of the reference cell. Therefore, even if the reference voltage is varied, variation in the difference between Vwlref and Vwl can be controlled because Vwlref is linked to Vwl.
Further, similar advantage may also be obtained by producing the word line voltages for both memory cells and reference cell at the programxe2x80xa2erasexe2x80xa2program verifyxe2x80xa2erase verify from two regulators and by applying another voltage VDDR to these word lines during the read.
According to a third aspect of the present invention, there is provided a non-volatile semiconductor memory which comprises a memory cell array having a plurality of non-volatile memory cells each having three or more threshold voltage levels;
word lines, bit lines and source lines connected to the memory cells;
a row decoder for selecting one of the word lines;
a column decoder for selecting one of the bit lines;
first and second reference cells;
first, second and third load current sources;
a first load circuit for providing a first voltage output from both a first load current and a current flowing through one of the bit lines by applying a first word line voltage to one of the word lines;
a second load circuit for providing a second voltage output from both a second load current and a current flowing through one of the bit lines by applying the first word line voltage to a word line of the first reference cells;
a first read circuit for deciding whether the memory cells are at one of first and second levels by comparing the first voltage output with the second voltage output;
a third load circuit for providing a third voltage output from both a third load current and a current flowing through one of the bit lines by applying the first word line voltage to a word line of the second reference cell; and
a second read circuit for deciding whether the memory cells are at one of second and third levels by comparing the second voltage output with the third voltage output;
wherein N1/N2 is larger than I1/I2 where N1 (N1xe2x89xa71, positive integer) is the number of the first reference cell connected in parallel with one another, N2 (N2xe2x89xa71, positive integer) is the number of the second reference cell connected in parallel with one another, I1 is the second load current and I2 is the third load current.
According to the third non-volatile memory, the stable read and verify can be executed for the temperature dependence of the cell current and for variation in the cell current by similarly setting the cell current of reference cells per load current to that of the memory cells.
Further, variation in the cell current for variation in the word line voltage can be controlled by increasing the load current of the reference cell having the highest threshold voltage more than the load current of the reference cell having the lowest threshold voltage.
Still further, a withstanding property for ground noise can be obtained by proportioning the number of data lines connected to load transistors at both the memory side and the reference side. In this case, the reference voltage is commonly input to all of the sense amplifiers.
According to a fourth aspect of the present invention, there is provided a non-volatile semiconductor memory which comprises a memory cell array having first and second non-volatile memory cells each having three or more threshold voltage levels;
word lines, bit lines and source lines connected to the memory cells;
a row decoder for selecting one of the word lines;
a column decoder for selecting one of the bit lines;
first to fourth reference cells;
first to sixth load current sources; and
first to third comparators;
wherein when a first mode signal is a first logic, the first memory cell and the first load current source are provided as a first input of the first comparator, the second memory cell and the second load current source are provided as a first input of the second comparator, and the first reference cell and the third load current source are provided as a common second input of the first and second comparators, so that the third comparator is set to an inactivated condition, respectively; and
wherein when the first mode signal is a second logic, one of the first and second memory cells is connected to one of the first and second load current sources, so that the connection node is provided as a first input of the first to third comparators, the second reference cell and the fourth load current source are provided as a second input of the first comparator, the third reference cell and the fifth load current source are provided as a second input of the second comparator, and the fifth reference cell and the sixth load current source are provided as a second input of the third comparator, respectively.
According to the fourth non-volatile semiconductor memory, a non-volatile memory switchable to multi-level and 2-level can be obtained by a command or program to ROM. Further, the number of the sense amplifiers can be minimized by switching with the multi-level mode or 2-level mode both a first switch for connecting a sense amplifier to a data line and a second switch for connecting a current load to the data line, respectively.
According to a fifth aspect of the present invention, there is provided a non-volatile semiconductor memory which comprises a memory cell array having a plurality of non-volatile memory cells each having three or more threshold voltage levels;
word lines, bit lines and source lines connected to the memory cells;
a row decoder for selecting one of the word lines;
a column decoder for selecting one of the bit lines;
an input/output buffer with N bits to which program data is input to provide read data as an output;
an input register with M bits for latching program data input by a plurality of cycles;
a test data generator for producing test data with K bits from input data of the M bits;
a column redundancy replacement circuit for replacing detective columns of L bits in the memory cell array;
a page buffer for latching output data of (M+K+L) bits from the column redundancy replacement circuit to which data of (M+K) bits is input; and
a program circuit for generating first or second program voltage whether data of the page buffer is non-program data.
According to a sixth aspect of the present invention, there is provided a non-volatile semiconductor memory which comprises a memory cell array having a plurality of non-volatile memory cells each having three or more threshold voltage levels;
word lines, bit lines and source lines connected to the memory cells;
a row decoder for selecting one of the word lines;
a column decoder for selecting one of the bit lines;
a read circuit for reading (M+K+L)bit-data front the memory cells;
a column redundancy replacement circuit for replacing detective columns of L bits in the memory cell array;
an error correction circuit for providing output data of (M+K) bits from the column redundancy replacement circuit to which data of (M+K+L) bits is input;
an output register for latching input data of M bits; and
an output buffer for providing M bits in the form of N bit-data by a plurality of cycles.
According to the fifth and sixth non-volatile semiconductor memories, the redundancy and error correction can be executed at the same time on the Flash memories because they include the input buffer for maintaining the programmed input data, the error correction circuit for generating test data for the error detection or correction from the input data, the redundancy replacement circuit for replacing the program data composed of the programmed input data and the test data, depending upon the column redundancy information, and the page buffer for latching the output from the redundancy replacement circuit.
Further, since the non-volatile semiconductor memories have the sense amplifiers for the verify and read, reading can be achieved from a block which is not an object of the program even if the program time becomes long by the multi-level state.
Still further, since the verify is executed with a plurality of cycles, the number of the sense amplifiers for the verify can be reduced as compared with the number of the sense amplifiers for the read, thereby suppressing the circuit area.
More further, since the error correction is carried out after the data read out from the memory cells is replaced depending upon the redundancy information, the redundancy and the error correction are executed on the Flash memories at the same time.
According to a seventh aspect of the present invention, there is provided a non-volatile semiconductor memory which comprises a memory cell array having a plurality of non-volatile memory cells;
word lines, bit lines and source lines connected to the memory cells;
a row decoder for selecting one of the word lines;
a column decoder for selecting one of the bit lines;
at least one reference cell; and
a comparator circuit for comparing a cell current of the reference cell with a cell current of selected one of memory cells;
wherein a first input of the comparator circuit is connected to the selected one of the memory cells when a first signal is a first logic, while the first input is connected to one of current sources selected from internal and external current sources when the first signal is a second logic; and
wherein a threshold voltage of the reference cell is controlled while monitoring an output voltage of the comparator circuit when the first signal is the second logic.
According to the seventh non-volatile semiconductor memory, as one constant current source is employed as a cell side input of the sense amplifier, Vt adjustment of the reference cell can be carried out while monitoring the output of the sense amplifier. Therefore, Vt control with high accuracy can be executed at a short time.
According to an eighth aspect of the present invention, there is provided a non-volatile semiconductor memory which comprises a memory cell array having a plurality of non-volatile memory cells each having three or more threshold voltage levels;
word lines, bit lines and source lines connected to the memory cells;
a row decoder for selecting one of the word lines; and
a column decoder for selecting one of the bit lines;
wherein when the three threshold voltage levels are given by Vt1, Vt2 and Vt3 (Vt1 less than Vt2 less than Vt3), respectively, the following steps (1) to (5) are executed to carry out a program operation,
(1) loading program data,
(2) the program for the memory cells to be given by Vt2 being accomplished by a first gate voltage,
(3) detecting whether the memory cells have Vt2, and carrying out the step (2) using a second gate voltage higher than the first gate voltage when they do not have Vt2, followed by a next step (4) when they have Vt2,
(4) the program for the memory cells to be given by Vt3 being carried out by a value equal to or higher (a third gate voltage) than a maximum value of a program gate voltage of the memory cells to be given by Vt2, and
(5) detecting whether the memory cells have Vt3, and re-executing the step (4) when they do not have Vt3, while finishing the program operation when they have Vt3.
According to a ninth aspect of the present invention, there is provided a non-volatile semiconductor memory which comprises a memory cell array having a plurality of non-volatile memory cells each having three or more threshold voltage levels;
word lines, bit lines and source lines connected to the memory cells;
a row decoder for selecting one of the word lines; and
a column decoder for selecting one of the bit lines;
wherein when the three threshold voltage levels are given by Vt1, Vt2 and Vt3 (Vt1 less than Vt2 less than Vt3), respectively, the following steps (1) to (5) are executed to carry out a program operation,
(1) loading program data,
(2) the program for the memory cells to be given by Vt3 being accomplished by a voltage value (a third gate voltage) equal to or higher than a maximum value of a program gate voltage of the memory cells to be given by Vt2,
(3) detecting whether the memory cells have Vt3, and re-executing the step (2) when they do not have Vt2, followed by a next step (4) when they have Vt2,
(4) the program for the memory cells to be given by Vt2 being carried cut by a first gate voltage, and
(5) detecting whether the memory cells have Vt2, and executing the step (4) using a second gate voltage higher than the first gate voltage when they do not have Vt2, while finishing the program operation when they have Vt2.
According to the eighth and ninth on-volatile memories, the program time can be reduced by dividing the program sequence into the first program of the highest level of Vt and the second program except it.
Further, at a first program verify for judging or detecting whether the memory cells have Vt2, the word line voltage of the selected memory cells is given as a first verify voltage, and the word line voltage of the reference cell is given by a second verify voltage which is lower than the first verify voltage. At a second program verify for judging whether the memory cells have Vt3, the word line voltage of the selected memory cells is given by a third verify voltage. Therefore, the word line voltage of the reference cell can be given as a second verify voltage.
According to a tenth aspect of the present invention, there is provided a non-volatile semiconductor memory which comprises a memory cell array having a plurality of non-volatile memory cells each having three or more threshold voltage levels;
word lines, bit lines and source lines connected to the memory cells;
a row decoder for selecting one of the word lines;
a column decoder for selecting one of the bit lines;
an input/output buffer to which program data is input to provide read data;
an input register with M bits for latching program data to be input;
a column redundancy replacement circuit for replacing defective columns of L bits in the memory cell array;
a page buffer for latching output data of (M+L) bits from the column redundancy replacement circuit to which data of M bits is input; and
a program circuit for generating one of first and second program voltages according to whether data of the page buffer is non-program data.
According to an eleventh aspect of the present invention, there is provided a non-volatile semiconductor memory which comprises a memory cell array having a plurality of non-volatile memory cells each having three or more threshold voltage levels;
word lines, bit lines and source lines connected to the memory cells;
a row decoder for selecting one of the word lines;
a column decoder for selecting one of the bit lines;
a read circuit for reading data of (M+L) bits from the memory cells;
a column redundancy replacement circuit for replacing defective columns of L bits in the memory cell array to provide M bits by the input of the data of (M+L) bits; and
an output buffer for providing the data of M bits output from the column redundancy replacement circuit.
According to a twelfth aspect of the present invention, there is provided a non-volatile semiconductor memory which comprises a memory cell array having a plurality of non-volatile memory cells each having three or more threshold voltage levels;
word lines, bit lines and source lines connected to the memory cells;
a row decoder for selecting one of the word lines;
a column decoder for selecting one of the bit lines;
at least one reference cell;
a read circuit for reading data of the memory cells by applying a first voltage to the word lines to compare a current flowing through the bit lines with a current flowing through the reference cell;
an erase circuit for erasing data of the memory cells by applying a voltage to at least one selected from the word lines, bit lines, source lines, and a semiconductor region including the memory cells; and
an erase verify circuit for comparing a cell current of selected memory cells with a cell current of the reference cell by applying the first voltage to the memory cells to be erased while applying a second voltage different from the first voltage to a word line of the reference cell.
According to a thirteenth aspect of the present invention, there is provided a non-volatile semiconductor memory which comprises a memory cell array having a plurality of non-volatile memory cells each having three or more threshold voltage levels;
word lines, bit lines and source lines connected to the memory cells;
a row decoder for selecting one of the word lines;
a column decoder for selecting one of the bit lines;
at least one reference cell;
a read circuit for reading data of the memory cells by applying a first voltage to the word lines to compare a current flowing through the bit lines with a current flowing through the reference cell;
a program circuit for programming data to the memory cells by applying a voltage to at least one selected from the word lines, bit lines, source lines, and a semiconductor region including the memory cells; and
a program verify circuit for comparing a cell current of selected memory cells with a cell current of the reference cell by applying the first voltage to the memory cells to be programmed while applying a second voltage different from the first voltage to a word line of the reference cell.
According to a fourteenth aspect of the present invention, there is provided a non-volatile semiconductor memory which comprises a memory cell array having a plurality of non-volatile memory cells each having four or more threshold voltage levels;
word lines, bit lines and source lines connected to the memory cells;
a row decoder for selecting one of the word lines; and
a column decoder for selecting one of the bit lines;
wherein when the four threshold voltage levels are given by Vt1, Vt2, Vt3 and Vt4 (Vt1 less than Vt2 less than Vt3 less than Vt4), respectively, the following steps (1) to (5) are executed to carry out a program operation,
(1) loading program data,
(2) programs for the memory cells to be given by Vt2 and for those to be given by Vt3 being accomplished by a first gate voltage,
(3) detecting whether the threshold voltages of the memory cells have Vt2 and Vt3, respectively, and re-executing the step (2) when they do not have Vt2 and Vt3, followed by a next step (4) when they have Vt2 and Vt3,
(4) the program for the memory cells to be given by Vt4 being carried out by a voltage value (a third gate voltage) equal to or higher than a maximum value of a program gate voltage of the memory cells to he given by one of Vt2 and Vt3, and
(5) detecting whether the memory cells given by Vt4 have the threshold voltage of Vt4, and re-executing the step (4) when they do not have Vt4, while finishing the program operation when they have Vt4.
According to a fifteenth aspect of the present invention, there is provided a non-volatile semiconductor memory which comprises a memory cell array having a plurality of non-volatile memory cells each having four or more threshold voltage levels;
word lines, bit lines and source lines connected to the memory cells;
a row decoder for selecting one of the word lines; and
a column decoder for selecting one of the bit lines;
wherein when the four threshold voltage levels are given by Vt1, Vt2, Vt3 and Vt4 (Vt1 less than Vt2 less than Vt3 less than Vt4), respectively, the following steps (1) to (5) are executed to carry out a program operation,
(1) loading program data,
(2) the program for the memory cells to be given by Vt4 being accomplished by a value (a third gate voltage) which is equal to or higher than a maximum value of a program gate voltage of the memory cells to be given by one of Vt2 and Vt3,
(3) detecting whether the threshold voltage of the memory cells to be given by Vt4 have Vt4, and re-executing the step (2) when they do not have Vt4, followed by a next step (4) when they have Vt4,
(4) the program for the memory cells to be given by Vt2 and Vt3 being carried out by the first gate voltage, and
(5) detecting whether the memory cells given by Vt2 and Vt3 nave the threshold voltage of Vt2 and Vt3, respectively, and re-executing the step (2) when they do not have Vt2 and Vt3, respectively, while finishing the program operations when they have Vt2 and Vt3.